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datasheet 9DBU0441 revision c 04/22/15 1 ?2015 integrated device technology, inc. 4 o/p 1.5v pcie gen1-2-3 zdb/fob w/zo=100ohms 9DBU0441 description the 9DBU0441 is a member of idt's 1.5v ultra-low-power (ulp) pcie family. it has integrated output terminations providing zo=100 ? for direct connection to 100 ? transmission lines. the device has 4 output enables for clock management, and 3 selectable smbus addresses. recommended application 1.5v pcie gen1-2-3 zero-del ay/fan-out buffer (zdb/fob) output features ? 4 ? 1-167mhz low-power (lp) hcsl dif pairs w/zo=100 ? key specifications ? dif cycle-to-cycle jitter <50ps ? dif output-to-output skew <75ps ? dif phase jitter is pcie gen1-2-3 compliant ? dif bypass mode additive phase jitter is <300fs rms for pcie gen3 ? dif bypass mode additive phase jitter <350fs rms for 12k-20mhz features/benefits ? direct connection to 100 ? transmission lines; saves 16 resistors compared to standard hcsl outputs ? 45mw typical power consumption in pll mode; eliminates thermal concerns ? spread spectrum (ss) compatible; allows ss for emi reduction ? oe# pins; support dif power management ? hcsl-compatible differential input; can be driven by common clock sources ? smbus-selectable features; opti mize signal integrity to application ? slew rate for each output ? differential output amplitude ? pin/software selectable pl l bandwidth and pll bypass; optimize pll to application ? outputs blocked until pll is locked; clean system start-up ? device contains default configuration; smbus interface not required for device control ? 3.3v tolerant smbus interface works with legacy controllers ? three selectable smbus addre sses; multiple devices can easily share an smbus segment ? space saving 32-pin 5x5mm vfqfpn; minimal board space block diagram control logic ^vhibw_bypm_lobw# ^ckpwrgd_pd# sdata_3.3 ss- compatible pll voe(3:0)# sclk_3.3 vsadr clk_in c l k _ i n # dif0 dif1 dif2 dif3 4
4 o/p 1.5v pcie gen1-2-3 zdb/fob w/zo=100ohms 2 revision c 04/22/15 9DBU0441 datasheet pin configuration smbus address selection table power management table power connections pll operating mode ^sadr_tri ^ckpwrgd_pd# gnd voe3# dif3# dif3 gnd vddo1.5 32 31 30 29 28 27 26 25 ^vhibw_bypm_lobw# 1 24 voe2# fb_dnc 2 23 dif2# fb_dnc# 3 22 dif2 vddr1.5 4 21 vdda1.5 clk_in 5 20 gnda clk_in# 6 19 dif1# gndr 7 18 dif1 gnddig 817voe1# 9 10111213141516 vdddig1.5 sclk_3.3 sdata_3.3 voe0# dif0 dif0# gnd vddo1.5 32-pin vfqfpn, 5x5 mm, 0.5mm pitch v prefix indicates internal 120kohm pull down resistor 9DBU0441 epad is gnd ^ prefix indicates internal 120kohm pull up resistor ^v prefix indicates internal 120kohm pull up and pull down resistor ( biased to vdd/2 ) sadr address 0 1101011 m 1101100 1 1101101 x x x state of sadr on first application of ckpwrgd_pd# + read/write bit true o/p comp. o/p 0 x x x low low off 1 running 0 x low low on 1 1 running 1 0 running running on 1 1 running 1 1 low low on 1 clk_in oex# pin pll difx ckpwrgd_pd# smbus oex bit 1. if bypass mode is selected, the pll will be off, and outputs will be running. vdd gnd 47 98 16, 25 15,20,26,30 21 20 input receiver analo g digital power note: epad on this device is not electrically connected to the die. it should be connected to ground for best thermal performance. dif outputs pll analog description pin number hibw_bypm_lobw# mode byte1 [7:6] readback byte1 [4:3] control 0 pll lo bw 00 00 mbypass0101 1 pll hi bw 11 11
revision c 04/22/15 3 4 o/p 1.5v pcie gen1-2-3 zdb/fob w/zo=100ohms 9DBU0441 datasheet pin descriptions pin# pin name type pin description 1 ^ vhibw_bypm_lob latched in trilevel input to select high bw, bypass or low bw mode. see pll operating mode table for details. 2fb_dnc dnc true clock of differential feedback. the feedback output and feedback input are connected internally on this pin. do not connect anything to this pin. 3 fb_dnc# dnc complement clock of differential feedback. the feedback output and feedback input are connected internally on this pin. do not connect anything to this pin. 4 vddr1.5 pwr 1.5v power for differential input clock (receiver). this vdd should be treated as an analog power rail and filtered appropriately. 5 clk_in in true input for differential reference clock. 6 clk_in# in complementary input for differential reference clock. 7 gndr gnd analog ground pin for the differential input (receiver) 8 gnddig gnd ground pin for digital circuitry 9 vdddig1.5 pwr 1.5v digital power (dirty power) 10 sclk_3.3 in clock pin of smbus circuitry, 3.3v tolerant. 11 sdata_3.3 i/o data pin for smbus circuitry, 3.3v tolerant. 12 voe0# in active low input for enabling dif pair 0. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 13 dif0 out differential true clock output 14 dif0# out differential complementary clock output 15 gnd gnd ground pin. 16 vddo1.5 pwr power supply for outputs, nominally 1.5v. 17 voe1# in active low input for enabling dif pair 1. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 18 dif1 out differential true clock output 19 dif1# out differential complementary clock output 20 gnda gnd ground pin for the pll core. 21 vdda1.5 pwr 1.5v power for the pll core. 22 dif2 out differential true clock output 23 dif2# out differential complementary clock output 24 voe2# in active low input for enabling dif pair 2. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 25 vddo1.5 pwr power supply for outputs, nominally 1.5v. 26 gnd gnd ground pin. 27 dif3 out differential true clock output 28 dif3# out differential complementary clock output 29 voe3# in active low input for enabling dif pair 3. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 30 gnd gnd ground pin. 31 ^ckpwrgd_pd# in input notifies device to sample latched inputs and start up on first high assertion. low enters power down mode, subsequent high assertions exit power down mode. this pin has internal pull-up resistor. 32 ^sadr_tri latched in tri-level latch to select smbus address. see smbus address selection table. 33 epad gnd connect epad to ground.
4 o/p 1.5v pcie gen1-2-3 zdb/fob w/zo=100ohms 4 revision c 04/22/15 9DBU0441 datasheet test loads driving lvds rs rs low-power hcsl differential output test load 2pf 2pf 5 inches zo=100 ? note: the device can drive transmission line lengths greater than those allowed by the pcie sig rs device rs zo driving lvds cc cc r7a r7b r8a r8b 3.3v lvds clock input driving lvds inputs receiver has termination receiver does not have termination r7a, r7b 10k ohm 140 ohm r8a, r8b 5.6k ohm 75 ohm cc 0.1 uf 0.1 uf vcm 1.2 volts 1.2 volts component value note
revision c 04/22/15 5 4 o/p 1.5v pcie gen1-2-3 zdb/fob w/zo=100ohms 9DBU0441 datasheet absolute maximum ratings stresses above the ratings listed below can cause permanent damage to the 9dbu044 1. these ratings, which are standard values for idt commercially rated parts, are stress ratings on ly. functional operation of the device at these or any other conditions above those indicated in the operational sections of th e specifications is not implied. exposure to absolute maximum rating conditions for ex tended periods can affect product reliability. electrical parame ters are guaranteed only over the recommended operating temperature range. electrical characteristi cs?clock input parameters parameter symbol conditions min typ max units notes supply voltage vddx -0.5 2 v 1,2 input voltage v in -0.5 v dd +0.5 v 1,3 input high voltage, smbus v ihsmb smbus clock and data pins 3.3 v 1 storage temperature ts -65 150 c 1 junction temperature tj 125 c 1 input esd protection esd prot human body model 2000 v 1 1 guaranteed by design and characterization, not 100% tested in production. 2 operation under these conditions is neither implied nor guaranteed. 3 not to exceed 2.0v. ta = t amb, supply voltages per normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max units notes input common mode voltage - dif_in v com common mode input voltage 200 725 mv 1 input swing - dif_in v swing differential value 300 1450 mv 1 input slew rate - dif_in dv/dt measured differentially 0.4 8 v/ns 1,2 input leakage current i in v in = v dd , v in = gnd -5 5 ua input duty cycle d tin measurement from differential wavefrom 45 50 55 % 1 input jitter - cycle to cycle j di fi n differential measurement 0 150 ps 1 1 guaranteed by design and characterization, not 100% tested in production. 2 slew rate measured through +/-75mv window centered around differential zero
4 o/p 1.5v pcie gen1-2-3 zdb/fob w/zo=100ohms 6 revision c 04/22/15 9DBU0441 datasheet electrical characteristics?input/supply /common parameters?normal operating conditions ta = t amb ; supply voltages per normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max units notes supply voltage vddx supply voltage for core and analog 1.425 1.5 1.575 v commmercial r ange 0 25 70 c 1 industrial range -40 25 85 c 1 input high voltage v ih single-ended inputs, except smbus 0.75 v dd v dd + 0.3 v input mid voltage v im single-ended tri-level inputs ('_tri' suffix) 0.4 v dd 0.6 v dd v input low voltage v il single-ended inputs, except smbus -0.3 0.25 v dd v i in single-ended inputs, v in = gnd, v in = vdd -5 5 ua i inp single-ended inputs v in = 0 v; inputs with internal pull-up resistors v in = vdd; inputs with internal pull-down resistors -200 200 ua f ib yp bypass mode 1 167 mhz 2 f i p ll 100mhz pll mode 60 100.00 110 mhz 2 pin inductance l p in 7nh1 c in logic inputs, except dif_in 1.5 5 pf 1 c i ndi f_i n dif_in differential clock inputs 1.5 2.7 pf 1,5 c ou t output pin capacitance 6 pf 1 clk stabilization t stab from v dd power-up and after input clock stabilization or de-assertion of pd# to 1st clock 1ms1,2 input ss modulation frequency pcie f modi npci e allowable frequency for pcie applications (triangular modulation) 30 33 khz input ss modulation frequency non-pcie f modi n allowable frequency for non-pcie applications (triangular modulation) 066khz oe# latency t latoe# dif start after oe# assertion dif stop after oe# deassertion 1 3 clocks 1,3 tdrive_pd# t drvpd dif output enable after pd# de-assertion 300 us 1,3 tfall t f fall time of single-ended control inputs 5 ns 2 trise t r rise time of single-ended control inputs 5 ns 2 smbus input low voltage v ilsmb 0.6 v smbus input high voltage v ihsmb v ddsmb = 3.3v, see note 4 for v ddsmb < 3.3v 2.1 3.3 v 4 smbus output low voltage v olsmb @ i pullup 0.4 v smbus sink current i pullup @ v ol 4ma nominal bus voltage v ddsmb bus voltage 1.425 3.3 v sclk/sdata rise time t rsmb (max vil - 0.15) to (min vih + 0.15) 1000 ns 1 sclk/sdata fall time t fsmb (min vih + 0.15) to (max vil - 0.15) 300 ns 1 smbus operating frequency f maxsmb maximum smbus operating frequency 400 khz 6 1 guaranteed by design and characterization, not 100% tested in production. 2 control input must be monotonic from 20% to 80% of input swing. input frequency 3 time from deassertion until outputs are >200 mv 4 for v ddsmb < 3.3v, v ihsmb >= 0.8xv ddsmb 5 dif_in input 6 the differential input clock must be running for the smbus to be active capacitance ambient operating temperature input current t amb
revision c 04/22/15 7 4 o/p 1.5v pcie gen1-2-3 zdb/fob w/zo=100ohms 9DBU0441 datasheet electrical characteristics? low-power hcsl outputs electrical characteristi cs?current consumption ta = t amb ; supply voltages per normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max units notes dv/dt scope averaging on, fast setting (100mhz) 1 2.4 3.5 v/ns 1,2,3 dv/dt scope averaging on, slow setting (100mhz) 0.7 1.7 2.5 v/ns 1,2,3 slew rate matching dv/dt slew rate matching, scope averaging on 9 20 % 1,2,4 voltage high v hi gh 630 750 850 7 voltage low v low -150 26 150 7 max voltage vmax 763 1150 7 min voltage vmin -300 22 7 vswing vswing scope averaging off 300 1448 mv 1,2 crossing voltage (abs) vcross_abs scope averaging off 250 390 550 mv 1,5 crossing voltage (var) -vcross scope averaging off 11 140 mv 1,6 2 measured from differential waveform 7 at default smbus settings. slew rate statistical measurement on single-ended signal using oscilloscope math function. (scope averaging on) mv measurement on single ended signal using absolute value. (scope averaging off) mv 1 guaranteed by design and characterization, not 100% tested in production. 3 slew rate is measured through the vswing voltage range centered around differential 0v. this results in a +/-150mv window arou nd differential 0v. 4 matching applies to rising edge rate for clock and falling edge rate for clock#. it is measured using a +/-75mv window centered on the average cross point where clock rising meets clock# falling. the median cross point is used to calculate the voltage thresh olds the oscilloscope is to use for the edge rate calculations. 5 vcross is defined as voltage where clock = clock# measured on a component test board and only applies to the differential risi ng edge (i.e. clock rising and clock# falling). 6 the total variation of all vcross measurements in any particular system. note that this is a subset of vcross_min/max (vcross absolute) allowed. the intent is to limit vcross induced modulation by setting -vcross to be smaller than vcross absolute. ta = t amb ; supply voltages per normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max units notes i ddr vddr @ 100mhz 4 6 ma 1 i dddi g vddig, all outputs @100mhz 0.125 0.25 ma 1 i ddao vdda+vddo, pll mode, all outputs @100mhz 25 30 ma 1 i ddrpd vddr, ckpwrgd_pd# = 0 0.1 0.3 ma 1,2,3 i dddi gpd vdddig, ckpwrgd_pd# = 0 0.1 0.2 ma 1,2 i ddaopd vdda+vddo, ckpwrgd_pd# = 0 0.5 1 ma 1,2 1 guaranteed by design and characterization, not 100% tested in production. 2 input clock stopped. 3 in bypass mode, the pll is off and iddao is ~50% of this value. operating supply current powerdown current
4 o/p 1.5v pcie gen1-2-3 zdb/fob w/zo=100ohms 8 revision c 04/22/15 9DBU0441 datasheet electrical characteristics?ou tput duty cycle, jitter, sk ew and pll characteristics electrical characteristics? phase jitter parameters ta = t amb ; supply voltages per normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max units notes -3db point in high bw mode (100mhz) 2.3 3.6 4.7 mhz 1,5 -3db point in low bw mode (100mhz) 1 1.6 2.5 mhz 1,5 pll jitter peaking t jpeak peak pass band gain (100mhz) 1.3 2.5 db 1 duty cycle t d c measured differentially, pll mode 45 50 55 % 1 duty cycle distortion t dcd measured differentially, bypass mode @100mhz -1 -0.6 0 % 1,3 t p dbyp bypass mode, v t = 50% 3400 4301 5200 ps 1 t p dpll pll mode v t = 50% 0 50 150 ps 1,4 skew, output to output t sk3 v t = 50% 37 50 ps 1,4 pll mode 24 50 ps 1,2 additive jitter in bypass mode 0.1 5 ps 1,2 1 guaranteed by design and characterization, not 100% tested in production. 2 measured from differential waveform 3 duty cycle distortion is the difference in duty cycle betw een the output and the input clock when the device is operated in bypass mode. 4 all outputs at default slew rate 5 the min/typ/max values of each bw setting track each other, i.e., low bw max will never occur with hi bw min. pll bandwidth bw skew, input to output jitter, cycle to cycle t jcyc-cyc ta = t amb ; supply voltages per normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max industry limit units notes t jp hpcieg1 pcie gen 1 30 58 86 ps (p-p) 1,2,3,5 pcie gen 2 lo band 10khz < f < 1.5mhz 0.9 1.4 3 ps (rms) 1,2,3,5 pcie gen 2 high band 1.5mhz < f < nyquist (50mhz) 2.1 2.6 3.1 ps (rms) 1,2,3,5 t jphpcieg3co m pcie gen 3 common clock architecture (pll bw of 2-4 or 2-5mhz, cdr = 10mhz) 0.5 0.6 1 ps (rms) 1,2,3,5 t jphpcieg3srn s pcie gen 3 separate reference no spread (srns) (pll bw of 2-4 or 2-5mhz, cdr = 10mhz) 0.5 0.6 0.7 ps (rms) 1,2,3,5 t jp hpcieg1 pcie gen 1 0.1 5 n/a ps (p-p) 1,2,3,5 pcie gen 2 lo band 10khz < f < 1.5mhz 0.1 0.5 n/a ps (rms) 1,2,3,4, 5 pcie gen 2 high band 1.5mhz < f < nyquist (50mhz) 0.1 0.3 n/a ps (rms) 1,2,3,4 t jphpcieg3 pcie gen 3 (pll bw of 2-4 or 2-5mhz, cdr = 10mhz) 0.2 0.3 n/a ps (rms) 1,2,3,4 t jph125m0 125mhz, 1.5mhz to 10mhz, -20db/decade rollover < 1.5mhz, -40db/decade rolloff > 10mhz 200 300 n/a fs (rms) 1,6 t jph125m1 125mhz, 12khz to 20mhz, -20db/decade rollover < 1.5mhz, -40db/decade rolloff > 10mhz 313 350 n/a fs (rms) 1,6 1 guaranteed by design and characterization, not 100% tested in production. 4 for rms figures, additive jitter is calculated by solving the following equation: additive jitter = sqrt[(total jitter)^2 - (i nput jitter)^2] 5 driven by 9fgu0831 or equivalent 6 rohde&schartz sma100 phase jitter, pll mode t jphpcieg2 additive phase jitter, bypass mode t jphpcieg2 2 see http://www.pcisig.com for complete specs 3 sample size of at least 100k cycles. this figures extrapolates to 108ps pk-pk @ 1m cycles for a ber of 1-12.
revision c 04/22/15 9 4 o/p 1.5v pcie gen1-2-3 zdb/fob w/zo=100ohms 9DBU0441 datasheet additive phase jitter plo t: 125m (12khz to 20mhz) rms additive jitter: 313fs
4 o/p 1.5v pcie gen1-2-3 zdb/fob w/ zo=100ohms 10 revision c 04/22/15 9DBU0441 datasheet general smbus serial interface information how to write ? controller (host) sends a start bit ? controller (host) sends the write address ? idt clock will acknowledge ? controller (host) sends the beginning byte location = n ? idt clock will acknowledge ? controller (host) sends the byte count = x ? idt clock will acknowledge ? controller (host) starts sending byte n through byte n+x-1 ? idt clock will acknowledg e each byte one at a time ? controller (host) sends a stop bit note: smbus address is latched on sadr pin. how to read ? controller (host) will send a start bit ? controller (host) sends the write address ? idt clock will acknowledge ? controller (host) sends the beginning byte location = n ? idt clock will acknowledge ? controller (host) will send a separate start bit ? controller (host) sends the read address ? idt clock will acknowledge ? idt clock will send the data byte count = x ? idt clock sends byte n+x-1 ? idt clock sends byte 0 through byte x (if x (h) was written to byte 8) ? controller (host) will need to acknowledge each byte ? controller (host) will send a not acknowledge bit ? controller (host) w ill send a stop bit index block write operation controller (host) idt (slave/receiver) tstart bit slave address wr write ack beginning byte = n ack data byte count = x ack beginning byte n x byte ack o oo oo o byte n + x - 1 ack pstop bit index block read operation controller (host) idt (slave/receiver) tstart bit slave address wr write ack beginning byte = n ack rt repeat start slave address rd read ack data byte count=x ack x byte beginning byte n ack o oo oo o byte n + x - 1 n not acknowledge pstop bit
revision c 04/22/15 11 4 o/p 1.5v pcie gen1-2-3 zdb/fob w/zo=100ohms 9DBU0441 datasheet smbus table: output enable register 1 byte 0 name control function type 0 1 default bit 7 1 bit 6 dif oe3 output enable rw low/low enabled 1 bit 5 dif oe2 output enable rw low/low enabled 1 bit 4 1 bit 3 dif oe1 output enable rw low/low enabled 1 bit 2 1 bit 1 dif oe0 output enable rw low/low enabled 1 bit 0 1 1. a low on these bits will overide the oe# pin and force the differential output low/low smbus table: pll operating mode and output amplitude control register byte 1 name control function type 0 1 default bit 7 pllmoderb1 pll mode readback bit 1 r latch bit 6 pllmoderb0 pll mode readback bit 0 r latch bit 5 pllmode_swcntrl enable sw control of pll mode rw values in b1[7:6] set pll mode values in b1[4:3] set pll mode 0 bit 4 pllmode1 pll mode control bit 1 rw 1 0 bit 3 pllmode0 pll mode control bit 0 rw 1 0 bit 2 1 bit 1 amplitude 1 rw 00 = 0.55v 01 = 0.65v 1 bit 0 amplitude 0 rw 10= 0.75v 11 = 0.85v 0 1. b1[5] must be set to a 1 for these bits to have any effect on the part. smbus table: dif slew rate control register byte 2 name control function type 0 1 default bit 7 1 bit 6 slewratesel dif3 slew rate selection rw slow setting fast setting 1 bit 5 slewratesel dif2 slew rate selection rw slow setting fast setting 1 bit 4 1 bit 3 slewratesel dif1 slew rate selection rw slow setting fast setting 1 bit 2 1 bit 1 slewratesel dif0 slew rate selection rw slow setting fast setting 1 bit 0 1 smbus table: frequency select control register byte 3 name control function type 0 1 default bit 7 1 bit 6 1 bit 5 0 bit 4 0 bit 3 0 bit 2 1 bit 1 1 bit 0 slewratesel fb adjust slew rate of fb rw slow setting fast setting 1 byte 4 is reserved and reads back 'hff reserved reserved reserved reserved reserved reserved reserved controls output amplitude see pll operating mode table reserved see pll operating mode table reserved reserved reserved reserved reserved reserved reserved reserved
4 o/p 1.5v pcie gen1-2-3 zdb/fob w/ zo=100ohms 12 revision c 04/22/15 9DBU0441 datasheet smbus table: revision and vendor id register byte 5 name control function type 0 1 default bit 7 rid3 r 0 bit 6 rid2 r 0 bit 5 rid1 r 0 bit 4 rid0 r 0 bit 3 vid3 r 0 bit 2 vid2 r 0 bit 1 vid1 r 0 bit 0 vid0 r 1 smbus table: device type/device id byte 6 name control function type 0 1 default bit 7 device type1 r 0 bit 6 device type0 r 1 bit 5 device id5 r 0 bit 4 device id4 r 0 bit 3 device id3 r 0 bit 2 device id2 r 1 bit 1 device id1 r 0 bit 0 device id0 r 0 smbus table: byte count register byte 7 name control function type 0 1 default bit 7 0 bit 6 0 bit 5 0 bit 4 bc4 rw 0 bit 3 bc3 rw 1 bit 2 bc2 rw 0 bit 1 bc1 rw 0 bit 0 bc0 rw 0 reserved reserved vendor id device id reserved byte count programming 000100 binary or 04 hex 00 = fgx, 01 = dbx zdb/fob, 10 = dmx, 11= dbx fob a rev = 0000 revision id 0001 = idt device type writing to this register will configure how many bytes will be read back, default is = 8 bytes.
revision c 04/22/15 13 4 o/p 1.5v pcie gen1-2-3 zdb/fob w/zo=100ohms 9DBU0441 datasheet marking diagrams notes: 1. ?lot? is the lot sequence number. 2. ?coo? denotes co untry of origin. 3. yyww is the last two digits of the ye ar and week that the part was assembled. 4. line 2: truncated part number 5. ?l? denotes rohs compliant package. 6. ?i? denotes industrial temperature range device. thermal characteristics ics bu0441al yyww coo lot ics d0441ail yyww coo lot parameter symbol conditions pkg typ value units notes jc junction to case 42 c/w 1 c/w 1 c/w 1 c/w 1 c/w 1 ja5 junction to air, 5 m/s air flow 27 c/w 1 1 epad soldered to board thermal resistance nlg32
4 o/p 1.5v pcie gen1-2-3 zdb/fob w/ zo=100ohms 14 revision c 04/22/15 9DBU0441 datasheet package outline and package dimensions (nlg32) ? use epad option 1
revision c 04/22/15 15 4 o/p 1.5v pcie gen1-2-3 zdb/fob w/zo=100ohms 9DBU0441 datasheet ordering information "lf" suffix to the part number are the pb-free configuration and are rohs compliant. ?a? is the device revision designator (wil l not correlate with the datasheet revision). revision history part / order number shipping packaging package temperature 9DBU0441aklf trays 32-pin vfqfpn 0 to +70 c 9DBU0441aklft tape and reel 32-pin vfqfpn 0 to +70 c 9DBU0441akilf trays 32-pin vfqfpn -40 to +85 c 9DBU0441akilft tape and reel 32-pin vfqfpn -40 to +85 c rev. initiator issue date description page # a rdw 7/14/2014 1. updated electrical tables with char data. 2. added an additive phase jitter plot. 3. added 12khz to 20mhz additive phase jitter spec. 4. updated amplitude control bit description s in byte 1. various b rdw 9/19/2014 updated smbus input high/low parameters conditions, max values, and footnotes. 6 c rdw 4/17/2015 1. updated pin out and pin descriptions to show epad on package connected to ground. 2. updated front page text to standard format for these devices. added explicit bullet indicated spread spectrum compatibility. 3. updated clock input parameters table to be consistent with pcie vswing parameter. 4. minor updates to front page text for family consistency. 5. add note about tpad to power connections table. 1-5
disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the right to modify the products and/or specifications d escribed herein at any time and at idt?s sole discretion. all information in this document, including descriptions of product features and performance, is subject to change without notice. performance spe cifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. the information co ntained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limi ted to, the suitab ility of idt?s products for any particular purpose, an implied war ranty of merchantability, or non-infringement of the intellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third pa rties. idt?s products are not intended for use in applications involvin g extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an idt product can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their o wn risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered trademarks of idt. product specification subject to change wi thout notice. other trademarks and service marks used herein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright ?2015 integrated device technology, inc.. all rights reserved. corporate headquarters 6024 silver creek valley road san jose, ca 95138 usa sales 1-800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com tech support email: clocks@idt.com

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